Reconfigurable dual-mode multiple stage operational amplifiers

ABSTRACT

A reconfigurable dual-mode multiple stage operational amplifier circuit includes a configurable portion that can be selectively configured to operate in either a one-pole mode or a two-pole mode. Different exemplary operational amplifier circuits are provided, some of which employ a compensation portion that can be selectively coupled to the configurable portion. For example, in the one-pole operating mode the compensation portion is decoupled from an output of the configurable portion. Conversely, in the two-pole operating mode the compensation portion is coupled to the output. The compensation portion is configured to stabilize a signal on the output. The configurable portion switches between operational modes in response to at least one control signal. The operational amplifier may include a pulse generating portion that is coupled to operatively control the configurable portion in response to the at least one control signal. Such an implementation negates the need for a compensation portion.

RELATED APPLICATIONS

[0001] This is a continuation of U.S. patent application Ser. No.09/861,246, filed May 18, 2001, which, as of Feb. 18, 2003, is now U.S.Pat. No. 6,522,199.

TECHNICAL FIELD

[0002] This invention relates to operational amplifiers, and moreparticularly to dual-mode multiple stage operational amplifiers.

BACKGROUND

[0003] Two-stage CMOS operational amplifiers are advantageous in manycircuits because they are able to provide a large transconductance, afast settling time and sufficiently high gain.

[0004] Two-stage operational amplifier techniques are well known.Certain common two-stage operational amplifiers include compensationcomponents, such as, for example, a nulling resistor, and/orpole-splitting capacitor, configured to generate a zero and separate adominant pole and a second order pole.

[0005] Compensating a two-stage operational amplifier presents achallenge in a CMOS process that does not include a capacitor layer. Onearea-effective way to create a capacitor, is to utilize the gatecapacitance of a MOSFET device with a formed channel. To keep thecompensation capacitor turned on, however, the voltage differencebetween the two operational amplifier stages needs to be larger than theMOSFET threshold voltage under all of the process, supply, andtemperature conditions. Such a solution may not be suitable for certaindevices.

[0006] Thus, there is a continuing need for improved operationalamplifiers that are suitable for implementation in a CMOS integratedcircuitry and perhaps other types of circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] A more complete understanding of the various methods andarrangements of the present invention may be had by reference to thefollowing detailed description when taken in conjunction with theaccompanying drawings wherein:

[0008]FIG. 1. is a block diagram depicting a device having variouscomponent circuits including a memory module that includes an interfacecell with output circuitry suitable for employing an operationalamplifier in accordance with certain implementations of the presentinvention.

[0009]FIG. 2 is a schematic diagram depicting an exemplary outputcircuit, as in FIG. 1.

[0010]FIGS. 3a-b are schematic diagrams depicting conventional two-stageoperational amplifiers having compensation circuits.

[0011]FIGS. 4a-b are simplified schematic diagrams depicting areconfigurable dual mode multiple stage operational amplifier having acompensation portion, in accordance with certain exemplaryimplementations of the present invention.

[0012]FIG. 5 is a time-line chart depicting exemplary controllingsignals for use with a reconfigurable dual mode multiple stageoperational amplifier, in accordance with certain other exemplaryimplementations of the present invention.

[0013]FIG. 6 is a block diagram depicting a pulse-generating portion ofa reconfigurable dual mode multiple stage operational amplifier, inaccordance with certain exemplary implementations of the presentinvention.

[0014]FIGS. 7a-b are simplified schematic diagrams depictingreconfigurable dual mode multiple stage operational amplifiers that donot require compensation portions, in accordance with certain exemplaryimplementations of the present invention.

[0015]FIGS. 8a-b are more detailed schematic diagrams depicting twodifferent reconfigurable dual mode multiple stage operationalamplifiers, as in FIGS. 4a-b, having compensation portions, inaccordance with certain exemplary implementations of the presentinvention.

[0016]FIGS. 9a-b are more detailed schematic diagrams depicting twodifferent reconfigurable dual mode multiple stage operationalamplifiers, as in FIGS. 7a-b, without compensation portions, inaccordance with certain further exemplary implementations of the presentinvention.

DETAILED DESCRIPTION

[0017]FIG. 1 is a block diagram depicting a device 100, e.g., a computeror like appliance, having a main circuit board 101 configured tointerconnect a memory device 102 to a processor 104, for example througha chip set 106. As depicted, memory device 102 includes an interfacecell 108. Interface cell 108 includes an output subsystem 110 having anoutput driver circuit 112.

[0018]FIG. 1 is just an exemplary implementation that includes an outputdriver circuit 112. Those skilled in the art will recognize that anoutput driver circuit 112′ may also be a separate circuit, or part ofanother circuit too. The description that follows will, however, focuson certain exemplary implementations of output driver circuit 112 asused in memory device 102, and more specifically on an operationalamplifier portion of output driver circuit 112.

[0019] In certain conventional output subsystems 112, output drivertransistors are arranged in a geometric series of legs allowing 27levels of output current. The legs of the output driver circuit 112 areformed by a plurality of two-transistor stacks (see, e.g., stack 210 inFIG. 2). Here, the bottom transistor is driven by an output pre-driverthat carries the output data.

[0020] The output subsystem circuit 112 shown in FIG. 2 is a simplifieddiagram of an output subsystem circuit having an operational amplifier200. Here, the output impedance of the output driver circuit 112 issignificantly controlled by a V_(ictrl) voltage on the upper transistorof the output stacks 210. Current control is accomplished by connectingthe gate nodes of the upper transistors to the outputs of the V_(gate)distribution circuit. The V_(gate) distribution circuit logicallycombines current control values and an enable signal to produce theoutput driver leg-enable signals. The leg-enable signals have a logic“1” voltage level equal to V_(gate) voltage. Here, the V_(gate) voltageis regulated by operational amplifier 200. In certain implementations, asingle operational amplifier is configured to regulate the V_(gate)voltage for nine output drivers within a byte.

[0021] As depicted in FIG. 2, output driver circuit 112 is shown as asingle two-transistor stack 210, wherein the bottom transistor is drivenby the predriver and the upper transistor is driven by V_(ictrl), whichis controlled by signal “Enable_b”. When the output driver is active,Enable_b is asserted, and V_(ictrl) is connected to V_(gate) throughPMOS transistor 204. When the output driver is inactive, Enable_b isde-asserted, and V_(ictrl) is discharged to ground through NMOStransistor 206. The capacitor “C_(decouple) 208 (e.g., 200-300 pF) isconfigured to minimize the noise on V_(ictrl).

[0022] Operational amplifier 200 is configured as a unity gain bufferthat regulates its output to a reference voltage V_(gRef). VoltageV_(gRef) is adjusted to an appropriate level to control the outputimpedance of output driver circuit 112. Capacitor C_(vgate) 212 at theoutput of operational amplifier 200 acts to stabilize the regulatingoperational amplifier.

[0023] When the signal Enable_b is asserted, V_(ictrl), is pulled fromground to the level of V_(gRef), within 10 nS. Operational amplifier 200has to be designed to have enough transconductance and a fast enoughsettling time to meet this timing requirement. Operational amplifier 200also needs to have enough gain to pull V_(ictrl) significantly close toV_(gRef).

[0024] A two-stage CMOS operational amplifier 200 is able to provide thelarge transconductance, fast settling time and high enough gain.

[0025] Two-stage operational amplifier techniques are well known andhave been published extensively. The most common technique is to use anulling resistor, pole-splitting capacitor and Miller effect, togenerate a zero and to separate the dominant pole and the second orderpole. For an exemplary reference, see MOS Operational Amplifier Design—Atutorial Overview, by Paul R. Gray and Robert G. Meyer, published in theIEEE Journal Of Solid State Circuits, Vol. SC-17, No. 6, pp. 969-982,Dec. 1982. This article is incorporated herein, by reference.

[0026] Exemplary schematics of a couple of conventional compensationtechniques are provided in FIGS. 3a-b. In FIG. 3a, exemplary operationalamplifier 200 includes a first stage 300 and a second stage 302. Here,the necessary compensation 304 is provided by a capacitor. Similarly,exemplary operational amplifier 200 in FIG. 3b includes compensation 304as provided by a resistor and capacitor.

[0027] Compensating a two-stage operational amplifier presents achallenge in a CMOS process that does not include a capacitor layer. Onearea-effective way to create a capacitor, however, is to utilize thegate capacitance of a MOSFET device with a formed channel. To keep thecompensation capacitor turned on, the voltage difference between the twooperational amplifier stages must be larger than the MOSFET thresholdvoltage under all of the process, supply, and temperature conditions.Using conventional compensation techniques, the dominant pole is createdby the compensation capacitance. Even with a Miller effect, thecompensation capacitance required to create a dominant pole is stilllarge enough when the operational amplifier drives a large loadcapacitance. It takes a large layout area to create a large compensationcapacitance by not using turned-on gate capacitance of a MOSFET devicein a CMOS process without a capacitor layer. As a result, in theprevious memory module designs to save layout area, the dominant pole iscreated from the loading of the operational amplifier. Contrary to othertechniques the compensation capacitance created a zero and a higherorder pole. The zero is used to improve the phase margin of theoperational amplifier. In this way, the compensation capacitance valueis greatly reduced, resulting in better layout area utilization.

[0028] With this in mind, in the output subsystem 112 of FIG. 2, todecouple the noise in V_(ictrl), the value of C_(decouple) 208 is about300 pF. Depending on whether Enable_b is asserted, regulatingoperational amplifier 200 sees different capacitances on its output andits dominant pole location varies greatly. For example, at certain times(i.e., when transistor 204 is on) operational amplifier 200 sees bothC_(vgate) 212 and C_(decouple) 208, while at other times (i.e., whentransistor 204 is off) it only sees C_(vgate) 212.

[0029] One possible approach is to design the operational amplifier suchthat it is well compensated with the minimum output load (i.e., whenEnable_b is de-asserted). However, this requires a large capacitancevalue for C_(vgate) 212, thereby resulting in higher power compensationand a greater layout area. This result would be unacceptable for manyapplications.

[0030] Thus, there is a need for an improved regulating operationalamplifier that is suitable for implementation in a CMOS integratedcircuitry and perhaps other types of circuitry.

[0031] The above stated need and others are satisfied by areconfigurable dual-mode multiple stage operational amplifier 400.Simplified diagrams are shown in FIGS. 4a-b. Here, operational amplifier400 changes modes of operation according to the position of threeswitches (SW1 406, SW2 408 and SW3 410).

[0032] As depicted in FIG. 4a, when SW1 406 is open, SW2 408 is closedand SW3 410 is connected to ground, operational amplifier 400 isconfigured in a single-pole mode.

[0033] As depicted in FIG. 4b, when SW1 406 is closed, SW2 408 is openand SW3 410 connects a compensation circuit 404 (e.g., similar to304/304′) between the outputs of the first and second stages,operational amplifier 400 is configured in a two-pole mode.

[0034] With reference once again to FIG. 2 (with operational amplifier400 substituted for operational amplifier 200), when the signal Enable_bis asserted, operational amplifier 400 will see a large output loading.In that case, operational amplifier 400 will be configured in thetwo-pole mode and stabilized by compensation circuit 404. When Enable_bis de-asserted, operational amplifier 400 will be placed in the one-polemode (with compensation circuit 404 disabled) to drive the resultingsmaller output loading.

[0035] In this arrangement, operational amplifier 400 will havesufficient phase margin in both modes and most of the capacitance can beplaced on V_(ictrl) to minimize noise. The resulting design is morerobust, and area and power efficient.

[0036] Furthermore, certain memory devices 102 (FIG. 1) have severalpower states for power saving features. For example, certainimplementations include an “active” mode in which operational amplifier400 is in a high power state and consumes more current. Operationalamplifier 400 can be placed in one-pole mode or two-pole mode dependingupon whether Enable_b is asserted. Thus, a high power state could besupported by placing operational amplifier 400 in a two-pole mode.Certain memory devices also have a “standby” mode, wherein operationalamplifier 400 could be placed in one-pole mode.

[0037] More detailed examples of such operational amplifiers aredepicted in FIGS. 8a-b.

[0038]FIG. 8a depicts an exemplary operational amplifier 800 having afirst stage 801, a second stage 802, a mirroring portion 804, and acompensation circuit 404. Here, with reference back to FIGS. 4a-b, SW1406 of is provided by transistors 806, SW2 408 is provided bytransistors 808, and SW3 410 is provided by transistors 810. Transistors806, 808 and 810 are each configured to be selectively configured byeither an Enable_b signal or the inverted version, Enable. Aconventional inversion process is depicted by inverter 812.

[0039]FIG. 8b depicts yet another exemplary implementation of anoperational amplifier having compensation circuit 404. Here, operationalamplifier 800′ is provided with a first stage 801′ that uses transistors814, 816 and 810 to act as SW1 406, SW2 408 and SW410, respectively.

[0040] Another important aspect of this novel type of reconfigurabledual-mode operational amplifier is that if a simple pulse generator isadded, the operational amplifier will work without a compensationcircuit.

[0041] If an appropriate width of pulse is generated from the edgeassertion of signal Enable_b, for example, the pulse can then be used toselectively configure the operational amplifier. A time-line diagramdepicting this signal generating process is provided in FIG. 5. Here, aconventional pulse generator 600, as depicted in the block diagram ofFIG. 6, generates a pulse signal 502 based on an edge detection ofEnable_b signal 500. Thus, during the assertion of the pulse, anoperational amplifier 700 (see, FIG. 7b) will be configured in thetwo-pole mode. In a two-pole mode, operational amplifier 700 exhibitslower output impedance and it can pull the output from ground to avoltage level close to V_(gRef). Since this configuration does not use acompensation circuit, operational amplifier 700 may not have asufficient phase margin and may ring around the final value at the endof the pulse. However, after the de-assertion of the pulse, operationalamplifier 700 (see FIG. 7a) will be configured in the one-pole mode andwill have a sufficient phase margin to settle its output to the finalvalue. Thus, eliminating the compensation circuit results in a verysimple and robust design.

[0042] With reference to the diagrams in FIGS. 7a-b, by removing thecompensation circuit, the design of operational amplifier 700 has beensimplified in that there are only two switches (SW1 704 and SW2 706) inthe first stage 701. Note that the second stage 702 is essentiallyunchanged from second stage 402, with the exception that there is nolonger the need for a connection to any compensation components.

[0043] More detailed examples of such alternative operational amplifiersare depicted in FIGS. 9a-b.

[0044]FIG. 9a depicts an exemplary operational amplifier 900 (without acompensation circuit) having a first stage 901, a second stage 902, anda mirroring portion 904. Here, SW1 704 of FIGS. 7a-b is provided bytransistors 906. Similarly, SW2 706 of FIGS. 7a-b is provided bytransistors 908. Transistors 906 and 908 are each arranged to beselectively configured by either a Pulse signal or the inverted version,Pulse_b. A conventional inversion process is depicted by inverter 910.

[0045]FIG. 9b depicts yet another exemplary implementation of anoperational amplifier without a compensation circuit. Here, operationalamplifier 900′ is provided with a first stage 901′ that uses transistors912 and 914 to act as SW1 704 and SW2 706, respectively.

[0046] Although the above examples have included PMOS and NMOStransistors, the techniques disclosed herein are also adaptable tocircuits having other types of transistors, e.g., bipolar transistors,etc.

[0047] Although some preferred implementations of the various methodsand arrangements of the present invention have been illustrated in theaccompanying Drawings and described in the foregoing DetailedDescription, it will be understood that the invention is not limited tothe exemplary implementations disclosed, but is capable of numerousrearrangements, modifications and substitutions without departing fromthe spirit of the invention as set forth and defined by the followingclaims.

What is claimed is:
 1. An operational amplifier circuit comprising aconfigurable portion that can be selectively configured to operate in atleast two operational modes including a one-pole mode and a two-polemode.
 2. The operational amplifier circuit as recited in claim 1,wherein the operational amplifier circuit is a multiple stageoperational amplifier and the configurable portion is provided in afirst stage.
 3. The operational amplifier circuit as recited in claim 1,further comprising a compensation portion that can be selectivelyoperatively coupled to the configurable portion, wherein when in theone-pole mode the configurable portion causes the compensation portionto be operatively decoupled from an output of the configurable portion.4. The operational amplifier as recited in claim 1, further comprising acompensation portion that can be selectively operatively coupled to theconfigurable portion, wherein when in the two-pole mode the configurableportion causes the compensation portion to be operatively coupled to anoutput of the configurable portion.
 5. The operational amplifier asrecited in claim 4, wherein the compensation portion is configured tostabilize a signal on the output of the configurable portion when theconfigurable portion is in the two-pole mode.
 6. The operationalamplifier as recited in claim 4, wherein the compensation portionchanges the impedance at the output of the configurable portion, whenthe configurable portion is in the two-pole mode.
 7. The operationalamplifier as recited in claim 1, wherein the configurable portion isconfigured to switch between the at least two operational modes inresponse to at least one control signal.
 8. The operational amplifier asrecited in claim 7, wherein the at least one control signal isselectively asserted by a circuit power controlling process.
 9. Theoperational amplifier as recited in claim 7, further including a pulsegenerating portion that is coupled to operatively control theconfigurable portion in response to the at least one control signal. 10.The operational amplifier as recited in claim 9, wherein the pulsegenerating portion is configured to cause the configurable portion to beplaced in the two-pole mode for a set period of time following a changein the at least one control signal.
 11. The operational amplifier asrecited in claim 10, wherein the pulse-generating portion is configuredto cause the configurable portion to be placed in the one-pole modeafter the set period of time.
 12. A dual mode multiple-stage operationalamplifier comprising: a first stage having a plurality of selectivelyenabled switching transistors configured to route signals to at leastone output node; and a second stage operatively and selectively coupledto the at least one output of the first stage via the selectivelyenabled switching transistors, and wherein the selectively enabledswitching transistors cause the operational amplifier to be selectivelyplaced in at least one of two different operational modes selected fromamong a one-pole mode and a two-pole mode.
 13. The dual mode multiplestage operational amplifier as recited in claim 12, further comprisingat least one compensation component that is configured to be selectivelycoupled between the output of the first stage and an input of the secondstage, and wherein the selectively enabled switching transistors causethe compensation component to place an impedance on the output of thefirst stage when the operational amplifier is placed in the two-polemode.
 14. The dual mode multiple stage operational amplifier as recitedin claim 13, wherein the selectively enabled switching transistors causethe compensation component to be electrically isolated from the outputof the first stage when the operational amplifier is placed in theone-pole mode.
 15. The dual mode multiple stage operational amplifier asrecited in claim 12, wherein the selectively enabled switchingtransistors are operatively controlled by at least one control signal.16. The dual mode multiple stage operational amplifier as recited inclaim 12, wherein the selectively enabled switching transistors includeCMOS transistors.
 17. A circuit comprising: an operational amplifierthat can be selectively configured to operate in at least twooperational modes including a one-pole mode and a two-pole mode; and atleast one output driver transistor coupled to an output of theoperational amplifier.
 18. The circuit as recited in claim 17, whereinthe operational amplifier and the at least one output driver transistorare each responsive to an enabling control signal.
 19. The circuit asrecited in claim 17, wherein the circuit is part of an interfacecircuit.
 20. The circuit as recited in claim 19, wherein the interfacecircuit is part of a memory module.
 21. A method for controlling theamount of electrical energy required in an operational amplifier, themethod comprising: providing an operational amplifier that can beselectively configured to operate in at least two operational modesincluding a one-pole mode and a two-pole mode; and setting theoperational amplifier to operate in the one-pole mode to save electricalenergy.